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74ACT74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

STMicroelectronics 

74ACT74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

s HIGH SPEED:

fMAX = 250MHz (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS

VIH = 2V (MIN.), VIL = 0.8V (MAX.)

s 50Ω TRANSMISSION LINE DRIVING

CAPABILITY

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74ACT74 is an advanced high-speed CMOS

DUAL D-TYPE FLIP FLOP WITH PRESET AND

CLEAR fabricated with sub-micron silicon gate

and double-layer metal wiring C2MOS tecnology.

A signal on the D INPUT is transferred to the Q

and Q OUTPUTS during the positive going

transition of the clock pulse.

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

DIP

SOP

TSSOP

TUBE

74ACT74B

74ACT74M

T&R

74ACT74MTR

74ACT74TTR

CLEAR and PRESET are independent of the

clock and accomplished by a low setting on the

appropriate input.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

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