MX93002FC Ver la hoja de datos (PDF) - Macronix International
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MX93002FC Datasheet PDF : 35 Pages
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MX93002
REGISTER 3
ADDRESS BIT
A2
A1
A0
DATA
0
1
1
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
POWER-ON
0
0
0
0
1
1
1
1
DESCRIPTION SWH
SWI
SWJ
SWK
ATT1 GAIN SETTING
( SWH ) D(7) = (1) : path of SWH is "CLOSE", D(7) = (0) : path of SWH is "OPEN”
( SWI ) D(6) = (1) : path of SWI is "CLOSE", D(6) = (0) : path of SWI is "OPEN"
( SWJ ) D(5) = (1) : path of SWJ is "CLOSE", D(5) = (0) : path of SWJ is "OPEN"
( SWK ) D(4) = (1) : path of SWK is "CLOSE", D(4) = (0) : path of SWK is "OPEN"
( ATT1 GAIN SETTING ) D(3~0) = (F)~(0) : - 45dB ~ 0dB; see NOTE 3
REGISTER 4
ADDRESS BIT A2
A1
A0
DATA
1
0
0
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
POWER_ON
0
1
0
1
1
0
0
0
DESCRIPTION
AD2-PGA GAIN SETTING
SWM RATE DATA FORMAT
( AD2-PGA GAIN SETTING ) D(7~4) = (0) ~ (F) : -6dB ~ 39dB; see NOTE 3
( SWM ) D(3) = (1) : path of SWM is "CLOSE", D(3) = (0) : path of SWM is "OPEN"
( RATE ) D(2) = (1) : master clock (MCLK) use 1.536MHz, D(2) = (0) : master clock (MCLK) use 2.048MHz
( DATA FORMAT ) D(1,0) = (1,1),(1,0) : Linear Coder/Decoder (16-bit format)
= (0,1) : a-Law Coder/Decoder (8-bit format)
= (0,0) : u-LAW Coder/Decoder (8-bit format)
@ Linear 16-bit format : 14-bit resolution with 2 LSB = 0
SIGN \ SCALE
POSITIVE
NEGATIVE
MIN
0000 0000 0000 0000
1111 1111 1111 1100
MAX
0111 1111 1111 1100
1000 0000 0000 0000
REGISTER 5
ADDRESS BIT
A2
A1
A0
DATA
1
0
1
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
POWER_ON
0
0
0
0
0
0
0
0
DESCRIPTION ALC1 SPKHI ADA AIADID DAYT ADYT ALC0 TDSPCK
D ( 5 ~ 2 and 0 ) : reserved
( SPKHI ) D(6) = (0) : SPKP/N can drive 8Ω load when SPK-DRV turns on
D(6) = (1) : SPKP/N appears high impedance (10KΩ) and SPK-DRV will keep a quiescent current when
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