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AD712

Dual Precision, Low Cost,High Speed, BiFET Op Amp

Analog Devices 

The photos of Figures 28a and 28b show the dynamic response

of the AD712 in the settling test circuit of Figure 29.

5V

100

90

10

0%

5mV

500ns

Figure 28a. Settling Characteristics 0 V to +10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

5V

100

90

10

0%

5mV

500ns

Figure 28b. Settling Characteristics 0 V to –10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)

Lower Trace: Amplified Error Voltage (0.01%/Div)

AD712

The input of the settling time fixture is driven by a flat-top pulse

generator. The error signal output from the false summing node

of A1 is clamped, amplified by A2 and then clamped again. The

error signal is thus clamped twice: once to prevent overloading

amplifier A2 and then a second time to avoid overloading the

oscilloscope preamp. The Tektronix oscilloscope preamp type

7A26 was carefully chosen because it does not overload with

these input levels. Amplifier A2 needs to be a very high speed

FET-input op amp; it provides a gain of 10, amplifying the error

signal output of A1.

GUARDING

The low input bias current (15 pA) and low noise characteristics

of the AD712 BiFET op amp make it suitable for electrometer

applications such as photo diode preamplifiers and picoampere

current-to-voltage converters. The use of a guarding technique

such as that shown in Figure 30, in printed circuit board layout

and construction is critical to minimize leakage currents. The

guard ring is connected to a low impedance potential at the

same level as the inputs. High impedance signal lines should not

be extended for any unnecessary length on the printed circuit

board.

TO-99 (H) PACKAGE

4

3

2

5

6

PLASTIC MINI-DIP (N) PACKAGE

CERDIP (Q) PACKAGE

AND SOIC (R) PACKAGE

4

5

6

3

2

7

8

1

7

1

8

Figure 30. Board Layout for Guarding Inputs

DATA

DYNAMICS

5109

(OR EQUIVALENT

FLAT TOP

PULSE

GENERATION)

5pF

HP2835

1/2

AD712

4.99k⍀

4.99k⍀

200⍀

5-18pF

10k⍀

VIN

10k⍀

1/2

AD712

5k⍀

0.47␮F

0.47␮F

–15V +15V

10k⍀

1.1k⍀

0.2-0.6pF

VOUT

10pF

0.1␮F

0.1␮F

VERROR ؋ 5

205⍀

TEKTRONIX 7A26

OSCILLOSCOPE

PREAMP

INPUT SECTION

1M⍀

HP2835

20pF

–15V +15V

Figure 29. Settling Time Test Circuit

REV. B

–9–

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