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LPC47N350-NE

Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface

SMSC -> Microchip 

Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface

Chapter 1 General Description

The LPC47N350 is a highly integrated LPC-based ACPI 2.0 and PC2001 compliant Keyboard, System,

and Power Management Controller for Notebook PC Applications. See Figure 1.1.

The LPC47N350 incorporates a high-performance 8051-based keyboard and system controller with

internal 64k byte Flash ROM; a hot-plug Docking LPC port; a Serial Peripheral Interface (SPI), four PS/2

ports; a real-time clock; a 16C550A-compatible 2 pin UART for Debug Port; two 8584-style I2C/SMBus

controllers with two selectable ports per controller; a Serial IRQ peripheral agent interface; an ACPI

Embedded Controller Interface; forty-one General Purpose I/O pins; four independently programmable

pulse width modulators; dual fan control through the implementation of two fan tachometer input pins;

and maskable hardware wake-up events.

The LPC47N350 has three separate power planes to provide “instant on” and system power

management functions. Additionally, the LPC47N350 incorporates sophisticated power control circuitry

(PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related

functions are supported through the SCI Interface.

The LPC47N350 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the

recommended functionality to support Windows 2000 and Windows Me. The I/O Address and Hardware

IRQ of each logical device in the LPC47N350 may be reprogrammed through the internal configuration

registers. There are 480 I/O address location options and 15 IRQ’s for each logical device.

nRESET_OUT

DLAD [3:0]

nDLFRAME

DSER_IRQ

nDCLKRUN

nDLDRQ[1]

LAD [3:0]

nLPCPD

nLFRAME

nLRESET

nLDRQ[1]

SYSTEM

RESET

DOCKING

LPC

INTERFACE

DOCKING

LPC

BUFFERS

AND

CONTROL

LPC BUS

HOST CPU

INTERFACE

VCC1(5)

VCC2(3)

VSS(8)

LPC47N350

CONFIGURATION REGISTERS

POWER

MANAGEMENT

nIRQ8*

nEC_SCI

nSMI*

SER_IRQ

nCLKRUN

PCI_CLK

INTERRUPTS

MODE

nEA, PGM, nFWP

VCC1_PWRGD

PWRGD

CLK_OUT

CLOCKI

(14.318 MHz)

32kHz_OUT

XOSEL

XTAL2

XTAL1

VCC0

AGND

CONTROL

INPUTS

PLL CLOCK

GENERATOR

RTC

2 x 128 BYTE

BANKS OF

CMOS RAM

BANK BANK

1

2

CONTROL, ADDRESS, DATA

nEC_SCI

ACPI

EMBEDDED

CONTROLLER

PM1

BLOCK

WDT

8051

256B Direct

RAM

Ring

Oscillator

w/ FAIL SAFE

MAILBOX REGISTERS

8051 SUB-BLOCK

EXTERNAL CONTROL

REGISTERS

EXTERNAL

8051 RAM

Executable RAM

Data RAM

FLASH ROM

VCC2 POWERED

Note: The block diagram should not used for pin count.

* -- ALTERNATE FUNCTION

VCC1 POWERED

8051TX*

8051RX*

3-26-02

16C550A

COMPATIBLE

SERIAL PORT

OUT

I/O

GENERAL I/O

PURPOSE I/O

INTERFACE I/O

I/O

I/O

LED DRIVER

16 x 8

KEYBOARD

INTERFACE

PS/2 PORTS

I2C/SMBus

I2C/SMBus

PWM

Fan Control

Serial

Peripheral

Interface (SPI)

Figure 1.1 LPC47N350 Block Diagram

TXD*

RXD*

OUT0, OUT1*, (OUT7-OUT11)*

GPIO0, GPIO1, GPIO2*, GPIO3, GPIO4*

GPIO5*, GPIO6, (GPIO7-GPIO9)*, GPIO10

(GPIO11-GPIO18)*, GPIO19, GPIO20*, GPIO21*

(SGPIO30-SGPIO33)*

LGPIO50-LGPIO53, LGPIO60-LGPIO63

nBAT_LED, nPWR_LED*, nFDD_LED*

KSI[0:7]

KSO[0:13], KSO[14:15]*

KBRST*, A20M*

KCLK, EMCLK, IMCLK, PS2CLK*

KDAT, EMDAT, IMDAT, PS2DAT*

AB1A_DATA, AB1A_CLK

AB1B_DATA, AB1B_CLK

AB2A_DATA *, AB2A_CLK *

AB2B_DATA *, AB2B_CLK *

PWM0*, PWM1*, PWM2*, PWM3*

FAN_TACH1*, FAN_TACH2*

SPCLK*

SPDOUT*

SPDIN*

SMSC LPC47N350

1

DATASHEET

Revision 1.1 (01-14-03)

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