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RC224ATLV

Embedded Modem Family

Conexant Systems 

2.0 Hardware Interface

2.1 Hardware Interface

RC224ATL/224ATLV

EmbeddedModem Family

2.1 Hardware Interface

2.1.1 Parallel Interface

Host Bus Interface

Interrupt Enable Register

(Addr=1, DLAB=0)

A 16450 UART-compatible parallel interface is provided.

Eight data lines, three address lines, and four control lines are supported.

The Interrupt Enable Register (IER) enables four types of interrupts that can

separately assert the HINT output. A selected interrupt can be enabled by setting

the corresponding enable bit to a logic 1, or disabled by resetting the

corresponding enable bit to a logic 0. All interrupt sources are disabled by setting

bits 0–3 to a logic 0. Disabling all interrupts inhibits the Interrupt Identifier

Register (IIR) and inhibits assertion of the HINT output. All other system

functions operate normally, including the setting of the Line Status Register

(LSR) and the Modem Status Register (MSR).

7

6

5

4

3

2

1

0

0

0

0

0

EDSSI

ELSI

ETBEI

ERBFI

Bits 4-7:

EDSSI

ELSI

ETBEI

ERBFI

Not used (always logic 0).

Enable Modem Status Interrupt. When this bit is a logic 1,

it enables assertion of the HINT output whenever bit 0, 1, 2, or

3 in the Modem Status Register (MSR) is a logic 1. When this

bit is a logic 0, it disables assertion of HINT due to setting of

any of these four MSR bits.

Enable Receiver Line Status Interrupt. When this bit is a

logic 1, it enables assertion of the HINT output when any

receiver status bit in the Line Status Register (LSR); i.e., bits

1, 2, 3, or 4, changes state. When this bit is a logic 0, it

disables assertion of HINT due to change of the receiver LSR

bits.

Enable Transmitter Holding Register Empty Interrupt.

When this bit is a logic 1, it enables assertion of the HINT

output when the Transmitter Holding Register Empty (THRE)

bit in the Line Status Register (LSR5) is set to a logic 1. When

this bit is a logic 0, it disables assertion of HINT due to LSR5.

Enable Received Data Available Interrupt. When this bit is

a logic 1, it enables assertion of the HINT output when

received data is available in the Receiver Buffer; i. e., the Data

Ready bit in the Line Status Register (LSR0) is a logic 1.

When this bit is a logic 0, it disables assertion of HINT due to

the LSR0.

2-6

Conexant

D224ATLVDSC

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