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USBUF01W6

EMI FILTER AND LINE TERMINATION FOR USB UPSTREAM PORTS

STMicroelectronics 

Fig. A5: USBUFxxW6 ESD clamping behavior

Rg

S1

Rt

S2

Rd

Vinput

Rd

VPP

VBR

Voutput

VBR

ESD Surge

USBUF01W6

Fig. A6: Measurement board

ESD

SURGE

16kV

Air

Discharge

TEST BOARD

Vin

Vout

USBUFxxW6

Rload

Device

to be

protected

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and

Rload>Rd, it gives these formulas:

Vinput = Rg.VBR + Rd.Vg

Rg

Voutput = Rt.VBR + Rd.Vinput

Rt

The results of the calculation done for Vg=8kV, Rg=330Ω (IEC61000-4-2 standard), VBR=7V (typ.)

and Rd = 1Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due

the low current involved after the resistance Rt.

The measurements done hereafter show very clearly (Fig. A7) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Voutput stage

- Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way

and -VF (forward voltage) in the negative way

5/9

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