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A49LF004

4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory

AMIC Technology 

Table 7: A/A Mux Mode Operation Selection

Mode

RST# OE# WE#

Read

Write

Standby

Output Disable

Reset

VIH

VIL

VIH

VIH

VIH

VIL

VIH

VIH

VIH

VIH

VIH

X

VIL

X

X

Product Identification

VIH

VIL

VIH

A49LF004

Address

AIN

AIN

X

X

X

A21 – A2 = X, A1 = VIL, A0 = VIL

A21 – A2 = X, A1 = VIL, A0 = VIH

A21 – A2 = X, A1 = VIH, A0 = VIH

I/O

DOUT

DIN

High Z

High Z

High Z

Manufacturer ID

Device ID

Continuation ID

Block-Erase Operation

The Block-Erase Operation allows the system to erase the

device in 64 KByte uniform block size for the A49LF004. The

Block-Erase operation is initiated by executing a six-byte

command load sequence for Software Data Protection with

Block-Erase command (30H or 50H) and block address. The

internal Block-Erase operation begins after the sixth WE# pulse.

The End-of-Erase can be determined using either Data# Polling

or Toggle Bit methods. See Figure 15 for timing waveforms.

Any commands written during the Block- Erase operation will

be ignored.

Chip-Erase

The A49LF004 device provides a Chip-Erase operation only in

A/A Mux mode, which allows the user to erase the entire

memory array to the ‘1’s state. This is useful when the entire

device must be quickly erased. The Chip-Erase operation is

initiated by executing a six-byte Software Data Protection

command sequence with Chip-Erase command (10H) with

address 5555H in the last byte sequence. The internal Erase

operation begins with the rising edge of the sixth WE#. During

the internal Erase operation, the only valid read is Toggle Bit or

Data# Polling. See Table 8 for the command sequence, Figure

16 for timing diagram, and Figure 21 for the flowchart. Any

commands written during the Chip-Erase operation will be

ignored.

Write Operation Status Detection

The A49LF004 device provides two software means to detect

the completion of a Write (Program or Erase) cycle, in

order to optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (I/O7) and

Toggle Bit (I/O6). The End-of-Write detection mode is enabled

after the rising edge of WE# which initiates the internal Program

or Erase operation. The actual completion of the nonvolatile

write is asynchronous with the system; therefore, either a Data#

Polling or Toggle Bit read may be simultaneous with the

completion of the Write cycle. If this occurs, the system may

possibly get an erroneous result, i.e., valid data may appear to

conflict with either I/O7 or I/O6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two times. If both reads are valid, then the device has

completed the Write cycle, otherwise the rejection is valid.

Data# Polling (I/O7)

When the A49LF004 device is in the internal Program operation,

any attempt to read I/O7 will produce the complement of the

true data. Once the Program operation is completed, I/O7 will

produce true data. Note that even though I/O7 may have valid

data immediately following the completion of an internal Write

operation, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent

successive Read cycles after an interval of 1 µs. During internal

Erase operation, any attempt to read I/O7 will produce a ‘0’.

Once the internal Erase operation is completed, I/O7 will

produce a ‘1’. The Data# Polling is valid after the rising edge of

fourth WE# pulse for Program operation. For Block- or Chip-

Erase, the Data# Polling is valid after the rising edge of sixth

WE# pulse. See Figure 12 for Data# Polling timing diagram.

Proper status will not be given using Data# Polling if the

address is in the invalid range.

Toggle Bit (I/O6)

During the internal Program or Erase operation, any

consecutive attempts to read I/O6 will produce alternating ‘0’s

and ‘1’s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will stop.

The device is then ready for the next operation. The Toggle Bit

is valid after the rising edge of fourth WE# pulse for Program

operation. For Block- or Chip-Erase, the Toggle Bit is valid after

the rising edge of sixth WE# pulse. See Figure 13 for Toggle Bit

timing diagram.

Data Protection

The A49LF004 device provides both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will not

initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited

when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the

Write operation. This prevents inadvertent writes during power-

up or power-down.

PRELIMINARY (November, 2003, Version 0.0)

11

AMIC Technology, Corp.

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