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A6850

Asynchronous Communications Interface Adapter

Altera Corporation 

a6850 Asynchronous Communications Interface Adapter Data Sheet

The transmit operation produces an interrupt (i.e., logic low on

nirq) when the following conditions all occur:

s Transmit interrupts are enabled.

s The tdre flag is set.

s The ncts signal is low.

The receive operation produces an interrupt when the following

conditions occur:

s Receive interrupts are enabled (i.e., the rie control signal is

high).

s Any one of the following signals is set: rdrf, ovr, or ndcd.

Variations &

Clarifications

Reset Operation

The a6850 is reset in one of two ways:

s Driving the nreset input low.

s Writing logic 1s into the cds bits of the control register.

The nreset input is used as an asynchronous clear to all internal

registers. Placing the a6850 into master reset will synchronously

clear the registers. However, master reset only works if both clocks

are running.

The following characteristics distinguish the Altera® a6850 from the

Motorola MC6850 device:

s The a6850 has separate input and output data buses, while the

MC6850 device has a single tri-state data bus.

s The nreset (asychronous reset) input on the a6850 is not

available in the Motorola MC6850 device.

s The a6850 bus interface was designed using synchronous

design techniques, allowing it to operate using various part

designations, speed grades, and optimization techniques.

s The a6850 requires that the txclk signal is always connected

to a free running clock, and that the e signal is high for at least

one txclk clock cycle when reading and writing data.

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Altera Corporation

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