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RS8235KHFD

Endstation ServiceSAR Controller

Conexant Systems 

RS8235HPI Hardware

Programming Interface

The RS8235 Hardware Programming Interface (HPI)

provides a set of fully-defined software primitives to

interface with an ATM UNI port based on the RS8235

SAR. It serves as an interface point for system software

designed to configure and manage the RS8235-based

UNI without the need for detailed manipulation of hard-

ware-related structures. It thus provides a layer of abstrac-

tion from the hardware for the system designer and user.

RS8235HPI primitives are used by higher-level application

software (such as network management and device

drivers) to obtain ATM services as required by their upper

protocol layers. These primitives handle SAR resource,

control and status management. The RS8235HPI performs

functions in the following categories:

• RS8235 SAR device initialization

• Memory resource allocation

• Resource management

• Connection management (including VCC setup

and teardown, and processing status)

• Segmentation/data transmission

• Data reception/reassembly

• Statistics gathering/error reporting

• Diagnostic testing

The RS8235HPI provides a reference implementation of

these critical functions in order to shorten the development

of a production-quality, customer system specific

ATM application.

The RS8235HPI is implemented in well-documented C

source code, specifically written to be highly portable

across a multiplicity of processors, compilers and

development environments.

RS8235 Endstation SAR

Special Features:

xBR Traffic Management

• TM 4.0 Service Classes

– CBR

– VBR (single, dual and CLP 0+1 leaky buckets)

– Real-time VBR

– ABR

– UBR

– GFC (controlled and uncontrolled flows)

– Guaranteed frame rate (GFR) (guaranteed

MCR on UBR VCCs)

• 8 Levels of priorities (8 + CBR)

• Dynamic per-VCC scheduling

• Multiple programmable ABR templates

(supplied by Conexant or user)

• Scheduler driven by local clock for low-jitter CBR

• Internal RM OAM cell feedback path

• Virtual FIFO rate matching

• Per-VCC MCR and ICR

• Tunneling

– VP tunnels (VCI interleaving on

PDU boundaries)

– CBR tunnels (cells interleaved on UBR

with an aggregate CBR limit)

Multi-Queue Segmentation Processing

• 4 Transmit queues with optional priority levels

• 4K VCCs maximum **

• AAL5 CPCS generation

• AAL0 Null CPCS (optional use of PTI for

PDU demarcation)

• ATM cell header generation

• Raw cell mode (52 octet)

• 200 Mbps half duplex

• 155 Mbps full duplex (with 2-cell PDUs)

• Message and streaming status modes

• Variable-length transmit FIFO-CDV-host

latency matching (1 to 9 cells)

• Symmetric Tx and Rx architecture

– Buffer descriptors

– Queues

• User-defined field circulates back to host (32 bits)

• Distributed host or SAR-shared

memory segmentation

• Simultaneous segmentation and reassembly

• Per-PDU control of CLP/PTI (UBR)

• Per-PDU control of AAL5 UU field

• Virtual Tx FIFO (PCI host)

Multi-Queue Reassembly Processing

• 4 reassembly queues

• 4K VCCs maximum **

• AAL5 CPCS checking

• AAL0

– PTI termination

– Cell count termination

• Early packet discard, based on:

– Receive buffer underflow

– Receive status overflow

– CLP with priority threshold

– AAL5 max PDU length

– Rx FIFO full

– Frame Relay DE with priority threshold

– LECID filtering for echo suppression

– Per-VCC firewalls

• Dynamic channel lookup (NNI or UNI addressing)

– Supports full address space

– Deterministic

– Flexible VCI count per VPI

– Optimized for signaling address assignment

• Message and streaming status modes

• Raw cell mode (52 octet)

• 200 Mbps half duplex

• 155 Mbps full duplex (with 2-cell PDUs)

• Distributed host or SAR-shared

memory reassembly

• 8 programmable reassembly hardware

time-outs (assignable per VCC)

• Global max PDU length for AAL5

• Per-VCC buffer firewall (memory usage limit)

• Simultaneous reassembly and segmentation

• Idle cell filtering

High-Performance Host Architecture

with Buffer Isolation

• Write-only control and status

• Read multiple command for data transfer

• Up to 4 host clients control and status queues

• Physical or logical clients

– Enables peer-to-peer architecture

• Descriptor-based buffer chaining

• Scatter/gather DMA

• Endian neutral

• Non-word (byte) aligned host buffer addresses

• Automatically detects presence of Tx data

or Rx free buffers

• Virtual FIFOs (PCI bursts treated as single address)

• Hardware indication of BOM

• Allows isolation of system resources

• Status queue interrupt delay

Designer Toolkit

• Evaluation module (RS8235/8251EVM)

• Reference schematics

• Hardware Programming Interface –

RS8235HPI reference source code (C)

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