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AD74322

Low Cost, Low Power Stereo Audio Analog Front End

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD74322

AD743xx

(SLAVE)

LRCLK/ DSDATA/ BCLK/ ASDATA/

SDIFS SDI

SCLK SDO SDOFS

AD743xx

(SLAVE)

LRCLK/ DSDATA/ BCLK/ ASDATA/

SDIFS SDI

SCLK SDO SDOFS

TFS

DT

DSP

(MASTER) SCLK

DR

RFS

PRELIMHINNIACRAYL Clock and Latch signals. The other method involves

C A creating a common Data In and Data Out buses where

E T each device has a common Clock but has separate Latch

T A signals which enable the devices on the bus at different

D times - either as a Time Division Multiplex (TDM) or

DACs (with I2S interfaces) to be interfaced to a cascade

of AD743xx devices. This allows extra flexibility in

choosing the number of input and out channels in the

cascade. The various (potential) modes for interfacing the

data ports of multiple devices are listed below:

software control.

DSP Mode - Daisy Chaining

Daisy Chain Mode

In Daisy Chain Mode, the serial registers (16-bit) of each device are

cascaded together by connecting the controller’s Data Out to CDIN of

the first device and the CDOUT of the first device to

CDIN of the next device (see Figure

<Control_Cascade_Daisy_Chain>). The CDOUT of the

final device is connected to the controller’s Data In. The

effective cascade length becomes 16 * N (where N is the

In this mode, sample data is passed along a daisychain of

I/O registers in a similar manner that used in the present

AD733xx devices. At the sample event each ADC result is

placed in the I/O register and is subsequently shifted

towards the DSP’s Rx register. This achieved by a

common SDIFS pulse which samples each device (enables

each device’s sample). {Drawback: as the device is stereo,

we would need to send 32 bits (or perhaps more) to the I/

number of devices in cascade) and each control word write

to each device requires 16 * N CCLK cycles. Please note

that the CLATCH pin of each device is driven from a

common controller output signal which must be active

during the entire 16 * N CCLK cycles as shown in Figure

<Control_Cascade_Timing_Daisy_Chain>.

TDM Mode

O register at each sample event.}

TDM Mode

In multiplexed mode, each device is programmed with its cascade

position. This allows devices to be enabled to the data buses only in their

appropriate time-slot as defined by the initial frame-sync

signal.

In TDM Mode, each device’s CDIN and CDOUT are commoned to the

controller’s Data Out and Data In respectively (see Figure

<Control_Cascade_TDM>). Each device’s CLATCH pin is separately

controlled. When CLATCH is disasserted activity on CDIN and CCLK

is not recognised and the CDOUT pin is tri-stated. Figure

<Control_Cascade_Timing_TDM> shows TDM Mode Control timing.

Data Port Cascading

The Data Port of the AD74322 is designed to allow

multiple single or dual channel devices to be cascaded

from a single DSP or controller serial port (SPORT).

There is also a mode which allows stereo ADCs and

Pr D 03/00

–15–

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