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AD7484BST

3MSPS, 14-Bit SAR ADC

Analog Devices 

7/13/01 5 PM

AD7484

PRELIMINARY TECHNICAL DATA

PARALLEL INTERFACE

The AD7484 features two parallel interfacing modes.

These modes are selected by the Mode pins as detailed in

Table 3.

Mode 2 Mode 1

Not Used

0

0

Parallel Mode 1

0

1

Parallel Mode 2

1

0

Not Used

1

1

Table 3. AD7484 Operating Modes

In Parallel Mode 1, the data in the output register is up-

dated and available for reading when BUSY returns high

at the end of a conversion. This mode should be used if

the conversion data is required immediately after the con-

version has completed. An example where this may be of

use is if the AD7484 were operating at much lower

throughput rates in conjunction with Nap Mode (for

power-saving reasons) and the input signal being com-

pared with set limits. If the limits were exceeded, the

ADC would then be woken up and commence sampling at

full speed. Figure 12 shows a timing diagram for the

AD7484 operating in Parallel Mode 1.

In Parallel Mode 2, the data in the output register is not

updated until the next falling edge of CONVST. This

mode could be used where a single sample delay is not

vital to the system operation. This may occur, for ex-

ample, in a system where a large amount of samples are

taken at high speed before a Fast Fourier Transform is

performed for frequency analysis of the input signal. Fig-

ure 13 shows a timing diagram for the AD7484 operating

in Parallel Mode 2.

Reading Data from the AD7484

Data is read from the part via a 15-bit parallel data bus

with the standard CS and RD signals. The CS and RD

signals are internally gated to enable the conversion result

onto the data bus. The data lines D0 to D14 leave their

high impedance state when both CS and RD are logic low.

Therefore, CS may be permanently tied logic low if re-

quired and the RD signal used to access the conversion

result. Figures 12 and 13 show timing specifications

called tQUIET and tQUIET2. The quiet time, tQUIET, is the

amount of time that should be left after any data bus activ-

ity before the next conversion is initiated. The second

quiet time, tQUIET2, is the period during a conversion where

activity on the data bus should be avoided. Reading a re-

sult from the AD7484 while the latter half of the

conversion is in progress will result in the degradation of

performance by about TBD dB.

Writing to the AD7484

The AD7484 features a user accessible offset register.

This allows the bottom of the transfer function to be

shifted by ±200mV. This feature is explained in more

detail in the Offset / Overrange section.

To write to the offset register a 15-bit word is written to

the AD7484 with the 12 LSBs containing the offset value

in 2’s complement format. The 3 MSBs must be set to

zero. The offset value must be within the range -1310 to

+1310, corresponding to an offset from -200mV to

+200mV. The value written to the offset register is stored

and used until power is removed from the device. The

value stored may be updated at any time between conver-

sions by another write to the device. Table 4 shows some

examples of offset register values and their effective offset

voltage. Figure 14 shows a timing diagram for writing to

the AD7484.

Code (De c) D14-D12 D11-D0 (2's Comp) Offset (mV)

-1310

000

101011100010

-200

-512

000

111000000000

-78.12

+256

000

000100000000

+39.06

+1310

000

010100011110

+200

Table 4. Offset Register Examples

Typical Connection

Figure 11 shows a typical connection diagram for the

AD7484 operating in Parallel Mode 1. Conversion is

initiated by a falling edge on CONVST. Once CONVST

goes low, the BUSY signal goes low and at the end of

conversion, the rising edge of BUSY is used to activate an

Interrupt Service Routine. The CS and RD lines are then

activated to read the 14 data bits (15 bits if using the

overrange feature).

In Figure 11 the VDRIVE pin is tied to DVDD, which results

in logic output levels being either 0 V or DVDD. The volt-

age applied to VDRIVE controls the voltage value of the

output logic signals. For example, if DVDD is supplied by

a 5 V supply and VDRIVE by a 3 V supply, the logic output

levels would be either 0 V or 3 V. This feature allows the

AD7484 to interface to 3 V devices while still enabling the

ADC to process signals at 5 V supply.

ANALOG

SUPPLY

1nF

10µF 0.1µF

47µF

4.75V - 5.25V

µC/µP

PARALLEL

INTERFACE

DVDD VDRIVE AVDD

RESET

MODE1

MODE2

WRITE

CLIP

NAP

STBY

VBIAS

REF3

0.1µF

REF2

0.1µF

REF1

0.47µF

0.47µF

AD7484

D0-D14

CS

CONVST

VIN

RD

BUSY

0V to

+2.5V

Figure 11. AD7484 Typical Connection Diagram

–10–

REV. PrC 7/13/01

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