ADM4850AR Ver la hoja de datos (PDF) - Analog Devices
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ADM4850AR Datasheet PDF : 16 Pages
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ADM4850–ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay tPLH, tPHL
Skew tSKEW
Rise/Fall Time tR, tF
Enable Time
Disable Time
Enable Time from Shutdown
RECEIVER
Propagation Delay tPLH, tPH
Differential Skew tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shut Down
Min Typ
115
600
600
4000
400
5
20
4000
50
330
Max
2500
70
2400
2000
2000
1000
255
50
50
3000
Unit
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
RL = 500 Ω, CL = 15 pF, Figure 7, ADM4850
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
CL = 15 pF, Figure 8
CL = 15 pF, Figure 8
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
ADM48501
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay tPLH, tPHL
Skew tSKEW
Rise/Fall Time tR, tF
Enable Time
Disable Time
Enable Time from Shutdown
RECEIVER
Propagation Delay tPLH, tPHL
Differential Skew tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shut Down
Min Typ
500
250
200
4000
400
5
20
4000
50
330
Max
600
40
600
1000
1000
1000
250
50
50
3000
Unit
kbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
RL = 500 Ω, CL = 15 pF, Figure 7, ADM4851
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
CL = 15 pF, Figure 8
CL = 15 pF, Figure 8
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4851
RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
ADM48511
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 4 of 16
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