ADM4850AR-REEL7 Ver la hoja de datos (PDF) - Analog Devices
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ADM4850AR-REEL7 Datasheet PDF : 16 Pages
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ADM4850–ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay tPLH, tPHL
Skew tSKEW
Rise/Fall Time tR, tF
Enable Time
Disable Time
Enable Time from Shutdown
RECEIVER
Propagation Delay tPLH, tPHL
Differential Skew tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shut Down
Min Typ
2.5
50
4000
55
5
20
4000
50
330
Max
180
50
140
180
180
190
50
50
50
3000
Unit
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4852
RL = 500 Ω, CL = 15 pF, Figure 7, ADM4852
RL =500 Ω, CL = 100 pF, Figure 7, ADM4852
CL = 15 pF, Figure 8
CL = 15 pF, Figure 8
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
ADM48521
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay tPLH, tPHL
Skew tSKEW
Rise/Fall Time tR, tF
Enable Time
Disable Time
Enable Time from Shutdown
RECEIVER
Propagation Delay tPLH, tPHL
Differential Skew tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shut Down
Min Typ
10
0
4000
55
5
20
4000
50
330
Max
30
10
30
35
35
190
30
50
50
3000
Unit
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853
RL = 500 Ω, CL = 15 pF, Figure 7, ADM4853
RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853
CL = 15 pF, Figure 8
CL = 15 pF, Figure 8
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
ADM48531
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 5 of 16
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