ADNS-2051 Ver la hoja de datos (PDF) - Avago Technologies

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ADNS-2051

Optical Mouse Sensor

Avago Technologies 

Read Operation

A read operation, which means that data is going from the

ADNS-2051 to the micro-controller, is always initiated by

the micro-controller and consists of two bytes. The first

byte contains the address, is written by the micro-con-

troller, and has a “0” as its MSB to indicate data direction.

The second byte contains the data and is driven by the

ADNS-2051. The transfer is synchronized by SCLK. SDIO is

changed on falling edges of SCLK and read on every rising

edge of SCLK. The micro-controller must go to a high Z

state after the last address data bit. The ADNS-2051 will

go to the high Z state after the last data bit (see detail “B”

in Figure 28). One other thing to note during a read

operation is that SCLK will need to be delayed after

the last address data bit to ensure that the ADNS-2051

has at least 100 µs to prepare the requested data. This is

shown in the timing diagrams below.

SCLK

CYCLE #

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

SDIO

0

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDIO DRIVEN BY MICRO-CONTROLLER

Figure 27. Read operation

DETAIL "A"

DETAIL "A"

SCLK

MICROCONTROLLER

TO ADNS-2051

SDIO HANDOFF

SDIO

A1

tHOLD

100 µs, MIN.

ADNS-2051 fig 27

60 ns, MIN.

0 ns, MIN.

A0

120 ns, MIN.

SDIO DRIVEN BY ADNS-2051

120 ns, MAX.

DETAIL "B"

120 ns, MAX.

Hi-Z

D7

D6

0 ns, MIN.

Figure 28. Microcontroller to ADNS-2051 SDIO handoff

DETAIL "B"

120 ns, MIN.

ADNS-2051 TO

MICROCONTROLLER

SDIO HANDOFF

SCLK

SDIO

AD1N0Sn-2s0, M51AfXig. 28

D0

R/W BIT OF NEXT ADDRESS

RELEASED BY 2051

DRIVEN BY MICRO

Figure 29. ADNS-2051 to microcontroller SDIO handoff

ADNS-2051 fig 29

Note:

The 120 ns high state of SCLK is the minimum

data hold time of the ADNS-2051. Since the

falling edge of SCLK is actually the start of

the next read or write command, the ADNS-

2051 will hold the state of D0 on the SDIO line

until the falling edge of SCLK. In both write

and read operations, SCLK is driven by the

micro-controller.

Serial port communications is not allowed

while PD (power down) is high. See

“Error Detection and Recovery” regarding re-

synchronizing via PD.

19

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