ADT7411ARQZ10 Ver la hoja de datos (PDF) - Analog Devices
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Lista de partido
ADT7411ARQZ10
Analog Devices
ADT7411ARQZ10 Datasheet PDF : 36 Pages
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Parameter1
CS to SCLK Hold Time, t7
CS to DOUT High Impedance, t8
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode)7
IDD (Power-Down Mode)
Power Dissipation
Min Typ
0
Max Unit
ns
40
ns
2.7
5.5
V
50
ms
3
mA
2.2
3
mA
10
µA
10
µA
10
mW
33
µW
Conditions/Comments
See Figure 3.
See Figure 3.
ADT7411
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V, VIH =VDD and VIL = GND.
VDD = 5 V, VIH = VDD and VIL = GND.
VDD = 3.3 V. Using normal mode.
VDD = 3.3 V. Using shutdown mode.
t1
SCL
t4
t2
t5
SDA
DATA IN
t3
SDA
DATA OUT
t6
Figure 2. I2C Bus Timing Diagram
CS
t1
t2
t7
SCLK
DIN
t3
t5
t6
t8
D7 D6 D5 D4 D3 D2 D1 D0 X
X
X
X
X
X
X
X
DOUT
t4
X
X
X
X
X
X
X
X D7 D6 D5 D4 D3 D2 D1
D0
Figure 3. SPI Bus Timing Diagram
200µA
IOL
TO
OUTPUT
PIN CL
50pF
200µA
IOH
1.6V
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
7 IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
Rev. A | Page 5 of 36
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