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5962-8501601YA

CMOS Priority Interrupt Controller

Intersil 

82C59A

Timing Waveforms (Continued)

RD/INTA

EN

CS

ADDRESS BUS

A0

DATA BUS

(1)

TAHRL

(3)

TRLRH

(18)

TRLEL

(14)

TRLDV

(20)

TAHDV

(19)

TRHEH

(2)

TRHAX

(15)

TRHDZ

FIGURE 13. READ/INTA

RD

INTA

WR

RD

INTA

WR

RD

INTA

WR

(11)

TRHRL

(12)

TWHWL

(13)

TCHCL

FIGURE 14. OTHER TIMING

(16)

TJHIH

IR

(9)

TJLJH

INT

INTA

SEE NOTE 1

SEE NOTE 3 SEE NOTE 4

DB

SEE

NOTE 2

(10)

TCVIAL

(10)

TCVIAL

CAS 0 - 2

(17)

(21)

TIALCV TCVDV

NOTES:

1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA.

2. During first INTA the Data Bus is not active in 80C86/88/286 mode.

3. 80C86/88/286 mode.

4. 8080/8085 mode.

FIGURE 15. INTA SEQUENCE

4-18

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