CY62146V(2002) Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Lista de partido
CY62146V Datasheet PDF : 10 Pages
| |||
CY62146V MoBL®
Parameter
R1
R2
RTH
VTH
3.0V
1105
1550
645
1.75
Unit
Ohms
Ohms
Ohms
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min. Typ.[3] Max. Unit
VDR
ICCDR
tCDR[4]
tR[5]
VCC for Data Retention)
Data Retention Current
Chip Deselect to Data
Retention Time
1.0
3.6
V
VCC= 1.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN <
0.3V; No input may exceed VCC + 0.3V
0
1 10 µA
ns
Operation Recovery Time
70
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min.)
VDR > 1.0 V
VCC(min.)
tCDR
tR
CE
Switching Characteristics Over the Operating Range [6]
70 ns
Parameter
Description
Min. Max. Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[9, 10]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[7, 8]
OE HIGH to High-Z[8]
CE LOW to Low-Z[7]
CE HIGH to High-Z[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
70
ns
70
ns
10
ns
70
ns
25
ns
5
ns
20
ns
10
ns
20
ns
0
ns
70
ns
35
ns
5
ns
20
ns
tWC
Write Cycle Time
70
ns
Notes:
5. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable VCC(min.) >10 µs.
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified
IOL/IOH and 30 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05159 Rev. *A
Page 4 of 10
Share Link: 