CY62147CV30LL-55BAI Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Lista de partido
CY62147CV30LL-55BAI Datasheet PDF : 14 Pages
| |||
CY62147CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Description
Min
Max
Min
Max
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE[10]
tHZBE
WRITE CYCLE[12]
Read Cycle Time
55
70
ns
Address to Data Valid
55
70
ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55
70
ns
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 11]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 11]
25
35
ns
5
5
ns
20
25
ns
10
10
ns
20
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
55
70
ns
BHE / BLE LOW to Data Valid
55
70
ns
BHE / BLE LOW to Low Z[9]
5
5
ns
BHE / BLE HIGH to High Z[9, 11]
20
25
ns
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tBW
BHE / BLE Pulse Width
50
60
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[9, 11]
WE HIGH to Low Z[9]
0
0
ns
20
25
ns
5
5
ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
10. If both byte enables are toggled together this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05202 Rev. *A
Page 6 of 14
Share Link: 