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CXB1582Q

Fibre Channel Receiver

Sony Semiconductor 

CXB1582Q

Pin

No.

Symbol

Type

Typical pin

I/O voltage

Equivalent circuit

VCCG

66

SYNCEN

TTL

input

TTL level

SYNCEN

VEET

VCCG

67 SDRSEL

TTL

input

TTL level

SDRSEL

VEET

VCCG

68 PPSEL

TTL

input

TTL level

PPSEL

VEET

Description

Byte sync enable

signal input.

When this pin is set

to high level,

+Comma (0011111)

or

–Comma (1100000)

is detected and the

parallel data is

synchronized to this

byte. (See the Timing

Charts.)

VEET When this pin is set

to low level, byte

synchronization is

not performed.

Serial data rate

selection.

Setting this pin to low

level selects

531.25Mbaud mode

and to high level

selects 1.0625Gbaud

mode.

VEET

Ping-Pong mode

selection.

When this signal is

set to high level

during 1.0625Gbaud

mode (SDRSEL =

high), parallel data is

output during Ping-

Pong mode. In other

words, byte 0 is

output in sync with

the rise of RBC0, and

VEET byte 1 with the rise of

RBC1. (See the

Timing Charts.)

– 10 –

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