FM25C160B(2014) Ver la hoja de datos (PDF) - Cypress Semiconductor

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FM25C160B
(Rev.:2014)

16-Kbit (2 K × 8) Serial (SPI) Automotive F-RAM

Cypress Semiconductor 

FM25C160B

Endurance

The FM25C160B devices are capable of being accessed at least

1013 times, reads or writes. An F-RAM memory operates with a

read and restore mechanism. Therefore, an endurance cycle is

applied on a row basis for each access (read or write) to the

memory array. The F-RAM architecture is based on an array of

rows and columns of 256 rows of 64-bits each. The entire row is

internally accessed once whether a single byte or all eight bytes

are read or written. Each byte in the row is counted only once in

an endurance calculation. Table 6 shows endurance calculations

for a 64-byte repeating loop, which includes an opcode, a starting

address, and a sequential 64-byte data stream. This causes

each byte to experience one endurance cycle through the loop.

Table 6. Time to Reach Endurance Limit for Repeating

64-byte Loop

SCK Freq

(MHz)

10

5

1

Endurance

Cycles/sec

18,660

9,330

1,870

Endurance

Cycles/year

5.88 × 1011

2.94 × 1011

5.88 × 1010

Years to Reach

Limit

17.0

34.0

170.1

Document Number: 001-86150 Rev. *A

Page 10 of 20

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