GL646USB Ver la hoja de datos (PDF) - GENESYS LOGIC

Número de pieza

componentes Descripción

Lista de partido

GL646USB

Three-in-one Scanner Controller for USB and 1394

GENESYS LOGIC 

BSMP(CDSCLK1)

SCLK

SENLOAD

MCLK(ADCCLK)

SDI

SDO

DBUS0~15

ABUS0~8

RASX

CASX

NOEX

NWEX

RASY

CASY

NOEY

NWEY

TSTMOD

TSTSEL0

TSTSEL1

MPU_SEL

MTR_SEL

IX1

IOX2

CKSEL

MPUCLOE

MPUCLK

EXTRST_

AVDD

AVSS

AGND

DVDD

DGND

GL646USB

This signal is applied synchronously with MCLK to specify the point of time that

the input is sampled.

Analog Device type : CDS image sampling clock

O

Analog Device type : Black level sampling clock

O

Serial interface clock output for Front-end

O

Serial interface data latch-in signal for Front-end

Wolfson type : Master clock.

This clock is applied at either six or three times the input pixel rate depending on

O

the operational mode.

Analog Device type: ADC Converter sampling clock

O

Serial interface data output signal for Front-end

I

Serial interface data input signal for Front-end

DRAM

B

DRAM data bus

O

DRAM address bus

O

DRAM RAS signal of first memory chip

O

DRAM CAS signal of first memory chip

O

DRAM OE(output enable) signal of first memory chip

O

DRAM WE signal of first memory chip

O

DRAM RAS signal of second memory chip

O

DRAM CAS signal of second memory chip

O

DRAM OE(output enable) signal of second memory chip

O

DRAM WE signal of second memory chip

Miscellaneous

Test mode selection pins :

{TSTMOD,TSTSEL0,TSTSEL1,MPU_SEL}=

I

0000 : mode1 0100 : mode2 0011 : mode3 0010 : mode4 0110 : mode5

100x : mode6 110x : mode7 101x : mode8 1110 : mode9

I

MTR_SEL=1 select Bi_polar

MTR_SEL=0 select Uni_polar

I

Clock input for crystal

O

Clock output for crystal

I

Scanner controller clock selection

O

Clock output

I

Hardware reset input

POWER

P

Analog power input

P

Analog ground input

P

Analog ground input for USB1.1

P

Digital power input

P

Digital ground input

Rev. 1.4

-10-

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