HD74LVCZ240AFPEL Ver la hoja de datos (PDF) - Renesas Electronics
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HD74LVCZ240AFPEL Datasheet PDF : 9 Pages
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HD74LVCZ240A
Octal Buffers / Line Drivers with 3–state Outputs
REJ03D0370–0300Z
(Previous ADE-205-229A (Z))
Rev.3.00
Jul. 30, 2004
Description
The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is an
inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four buffers.
When VCC is between 0 and 1.5 V, the device is in the high impedance state during power up or power down.
Low voltage and high-speed operation is suitable at battery drive product (note type personal computer) and low power
consumption extends the life of a battery for long time operation.
Features
• VCC = 2.7 to 5.5 V
• All inputs VIH (Max) = 5.5 V (@VCC = 0 to 5.5 V)
• All outputs VO (Max) = 5.5 V (@VCC = 0 V or output off state)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High impedance state during power up and power down
• Power off disables outputs, permitting live insertion
• High output current ±24 mA (@VCC = 3.0 to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LVCZ240AFPEL SOP–20 pin (JEITA) FP–20DAV
FP
HD74LVCZ240ATELL TSSOP–20 pin
TTP–20DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
G
A
H
X
L
H
L
L
H: High level
L: Low level
X: Immaterial
Z: High impedance
Output Y
Z
L
H
Rev.3.00 Jul. 30, 2004 page 1 of 8
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