HY57V56820CLT Ver la hoja de datos (PDF) - Hynix Semiconductor

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HY57V56820CLT

4 Banks x 8M x 8Bit Synchronous DRAM

Hynix Semiconductor 

FUNCTIONAL BLOCK DIAGRAM

8Mbit x 4banks x 8 I/O Synchronous DRAM

HY57V56820C(L)T

Self refresh logic

& timer

Internal Row

counter

CLK

CKE

CS

RAS

CAS

WE

DQM

Row active

Row

Pre

Decoders

refresh

Column

Active

Column

Pre

Decoders

8Mx8 Bank3

8Mx8 Bank2

8Mx8 Bank1

8Mx8 Bank0

Memory

Cell

Array

Y decoders

Bank Select

Column Add

Counter

A0

Address

A1

Registers

Burst

Counter

DQ0

DQ1

DQ6

DQ7

A12

BA0

BA1

Mode Registers

CAS Latency

Data Out Control Pipe Line Control

Rev. 0.4 / July 2003

3

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