HY57V658020B Ver la hoja de datos (PDF) - Hynix Semiconductor

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Lista de partido

HY57V658020B

4 Banks x 2M x 8Bit Synchronous DRAM

Hynix Semiconductor 

PIN CONFIGURATION

VDD 1

DQ0 2

VDDQ 3

NC 4

DQ1 5

VSSQ 6

NC 7

DQ2 8

VDDQ 9

NC 10

DQ3 11

VSSQ 12

NC 13

VDD 14

NC 15

/WE 16

/CAS 17

/RAS 18

/CS 19

BA0 20

BA1 21

A10/AP 22

A0 23

A1 24

A2 25

A3 26

VDD 27

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

54

VSS

53

DQ7

52

VSSQ

51

NC

50

DQ6

49

VDDQ

48

NC

47

DQ5

46

VSSQ

45

NC

44

DQ4

43

VDDQ

42

NC

41

VSS

40

NC

39

DQM

38

CLK

37

CKE

36

NC

35

A11

34

A9

33

A8

32

A7

31

A6

30

A5

29

A4

28

VSS

HY57V658020B

PIN DESCRIPTION

PIN

CLK

CKE

CS

BA0, BA1

A0 ~ A11

RAS, CAS, WE

DQM

DQ0 ~ DQ7

VDD/VSS

VDDQ/VSSQ

NC

PIN NAME

Clock

Clock Enable

Chip Select

Bank Address

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

Data Input/Output Mask

Data Input/Output

Power Supply/Ground

Data Output Power/Ground

No Connection

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

RAS, CAS and WE define the operation

Refer function truth table for details

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power supply for internal circuits and input buffers

Power supply for output buffers

No connection

Rev. 1.6/Nov. 01

2

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