ISP1181 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

fabricante

ISP1181

Full-speed Universal Serial Bus interface device

Philips Electronics 

Philips Semiconductors

ISP1181

Full-speed USB interface

Table 6: Memory configuration example

Physical size

(bytes)

Logical size

(bytes)

Endpoint description

64

64

control IN (64 byte fixed)

64

64

control OUT (64 byte fixed)

2046

1023

double-buffered 1023-byte isochronous endpoint

16

16

16-byte interrupt OUT

16

16

16-byte interrupt IN

128

64

double-buffered 64-byte bulk OUT

128

64

double-buffered 64-byte bulk IN

9.3 Endpoint initialization

In response to the standard USB request Set Interface, the firmware must program all

16 ECRs of the ISP1181 in sequence (see Table 4), whether the endpoints are

enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been configured successfully, the firmware must return an empty

packet to the control IN endpoint to acknowledge success to the host. If there are

errors in the endpoint configuration, the firmware must stall the control IN endpoint.

When reset by hardware or via the USB bus, the ISP1181 disables all endpoints and

clears all ECRs, except for the control endpoint which is fixed and always enabled.

Endpoint initialization can be done at any time; however, it is valid only after

enumeration.

9.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The

firmware then responds to the interrupt and selects the endpoint for processing.

The endpoint interrupt bit will be cleared by reading the Endpoint Status Register

(ESR). The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from

ISP1181 using the Read Buffer command. When the whole packet has been read,

the firmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written

to ISP1181 using the Write Buffer command. When the whole packet has been

written to the buffer, the firmware sends a Validate Buffer command to enable data

transmission to the host.

9.5 Special actions on control endpoints

Control endpoints require special firmware actions. The arrival of a SETUP packet

flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for

the control IN and OUT endpoints. The microcontroller needs to re-enable these

commands by sending an Acknowledge Setup command to both control endpoints.

9397 750 06896

Objective specification

Rev. 01 — 13 March 2000

© Philips Electronics N.V. 2000. All rights reserved.

12 of 69

Share Link: