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ISP1181

Full-speed Universal Serial Bus interface device

Philips Electronics 

Philips Semiconductors

ISP1181

Full-speed USB interface

This ensures that the last SETUP packet stays in the buffer and that no packets can

be sent back to the host until the microcontroller has explicitly acknowledged that it

has seen the SETUP packet.

10. DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to

another in a computer system, without intervention of the central processor (CPU).

Many different implementations of DMA exist. The ISP1181 supports two methods:

• 8237 compatible mode: based on the DMA subsystem of the IBM personal

computers (PC, AT and all its successors and clones); this architecture uses the

Intel 8237 DMA controller and has separate address spaces for memory and I/O

• DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single address space for both memory and I/O.

The ISP1181 supports DMA transfer for all 14 configurable endpoints (see Table 4).

Only one endpoint at a time can be selected for DMA transfer. The DMA operation of

the ISP1181 can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

• Single-cycle or burst transfers (up tot 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,

short/empty packet

• Programmable signal levels on pins DREQ, DACK and EOT

• Automatic DMA counter reload and transfer restart following EOT.

10.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA

Configuration Register, as shown in Table 7. The transfer direction (read or write) is

automatically set by bit EPDIR in the associated ECR, to match the selected endpoint

type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint specified in the DMA

Configuration Register, regardless of the current endpoint used for I/O mode access.

Table 7: Endpoint selection for DMA transfer

Endpoint

identifier

EPIDX[3:0]

Transfer direction

EPDIR = 0

EPDIR = 1

1

0010

OUT: read

IN: write

2

0011

OUT: read

IN: write

3

0100

OUT: read

IN: write

4

0101

OUT: read

IN: write

5

0110

OUT: read

IN: write

6

0111

OUT: read

IN: write

7

1000

OUT: read

IN: write

9397 750 06896

Objective specification

Rev. 01 — 13 March 2000

© Philips Electronics N.V. 2000. All rights reserved.

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