ILC1232 Ver la hoja de datos (PDF) - Impala Linear Corporation
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ILC1232 Datasheet PDF : 5 Pages
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ILC1232 mP Supervisory Circuit
Sept 1999
Pin Functions
Pin
Number
1
Pin
Name
PBRST
2
TD
3
TOL
4
GND
5
RST
6
RST
7
ST
8
VCC
Description
Pushbutton reset input. This input is debounced and can be driven with
external logic signals or a mechanical push button to actively force a reset.
All pulses less than 1ms in duration on the PBRST pin are ignored. Any
pulse with a duration of 20ms or greater is guaranteed to cause a reset.
Time delay input. This input selects the timebase used by the watchdog
timer. When TD = 0V, the watchdog timeout period is set to a nominal
value of 150ms, when TD = open, the watchdog timeout period is set to a
nominal value of 600ms and when TD = VCC, the watchdog timeout period
is 1.2 sec nominally.
Tolerance select input. Selects whether 5% or 10% of VCC is used as the
reset threshold voltage. When TOL = 0 V, the 5% tolerance level is
selected and when TOL = VCC, a 10% tolerance level is selected.
Ground pin, 0V reference.
RST is asserted high if either VCC goes below the reset threshold, the
watchdog times out or PBRST is pulled low for a minimum of 20ms. RST
remains asserted for one reset timeout period after VCC exceeds the reset
threshold or after the watchdog times out or after PBRST goes high.
RST is asserted low if either VCC goes below the reset threshold, the
watchdog times out or PBRST is pulled low for a minimum of 20ms. RST
remains asserted for one reset timeout period after VCC exceeds the reset
threshold or after the watchdog times out or after PBRST goes high.
Open-drain output.
Input to the watchdog timer. If ST does not see a transition from high to
low within the watchdog timeout period, RST and RST will be asserted.
Power supply input, 5V.
Block Diagram
VCC 8
Trip Point
Select
+
-
TOL 3
Ref
PBRST 1
Manual Reset
Debounce
ST 7
TD 2
Timeout
Select
Reset
Generator
Watchdog
Timer
6 RST
5 RST
4 GND
Impala Linear Corporation
ILC1232 1.1
(408) 574-3939 www.impalalinear.com
June 1999 3
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