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LT3710

Secondary Side Synchronous Post Regulator

Linear Technology 

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OPERATIO

To generate isolated multiple outputs, most systems use

either multiple secondary windings or cascade regulators

for each additional output. Multiple secondary windings

sacrifice regulation of the auxiliary outputs. Cascaded

regulators require a larger inductor for the main output,

because all of the power is processed in series.

By generating the auxiliary output(s) from the secondary

winding of the main output, the LT3710 allows for parallel

processing of the output power. This minimizes the main

output inductor size and directly regulates the auxiliary

output. With synchronous rectification, the system effi-

ciency is greatly improved.

Refering to the Block Diagram, the LT3710 basic functions

include a voltage amplifier, VA, to regulate the output

voltage to within typically 1.5%, a voltage mode PWM with

trailing edge synchronization and leading edge modula-

tion, a current limit amplifier, CA1, and high speed syn-

chronous switch drivers.

During normal operation (see Figure 2), a switching cycle

begins at the falling edge of the transformer secondary

voltage VS. The internal oscillator is reset, turning off the

top MOSFET M1 and turning on the bottom MOSFET M2.

During this portion of the cycle, the inductor current is

discharged by the output voltage VOUT2. The transformer

secondary voltage VS will go high during this portion of the

cycle. Since M1 is off, the switch node voltage VSW

remains zero. The inductor current continues to be dis-

charged by the output voltage VOUT2. This condition lasts

LT3710

until the ramp signal intersects the feedback error ampli-

fier output VAOUT. The top MOSFET M1 turns on, pulling

the switch node voltage to VS. The inductor current of the

LT3710 circuit is then charged by VS – VOUT2. The effective

on time of this buck circuit ends when the secondary

voltage becomes zero. The next cycle repeats.

The ideal equation for duty cycle of the LT3710 is:

D2 = VOUT2/VSP

where VOUT2 is the auxiliary output voltage, VSP is the

amplitude of the secondary voltage and D2 is the duty

cycle of the switching node voltage VSW, as defined in

Figure 2.

VRESET

T

D1T

TRANSFORMER

SECONDARY VOLTAGE

VS

VSP

SYNC SIGNAL VRESET

RAMP VCSET

VAOUT

TGATE

BGATE

IL

T

SWITCH NODE VSW

D2T

VSP

3710 F02

Figure 2. Leading Edge Modulation,

Trailing Edge Synchronization

APPLICATIO S I FOR ATIO

Synchronization and Oscillation Frequency Setting

The switching is synchronized to the secondary winding

falling edge and the synchronization threshold is typically

2.5V. The synchronization falling edge triggers an internal

inverted ramp (see Figure 2) and starts a new switching

cycle for the leading edge voltage mode PWM. The reason

for using leading edge modulation is to keep the trans-

former primary side peak current sensing undisturbed.

For proper synchronization, the oscillator frequency should

be set lower than the system switching frequency with

tolerances taken into account.

fOSC < (fSL • 0.8)

fSL is the low limit of the system switching frequency and

0.8 is the tolerance of fOSC.

For example, a system of 200KHz with 15% tolerance,

then fSL = 200k • 85% = 170kHz; and fOSC < (170k • 0.8),

fOSC should be set below 136kHz.

Once fOSC is determined, CSET can be calculated by

CSET = (107250pf/fOSC(kHz)) – 50pF.

For fOSC = 100kHz, CSET = 1022.5pF.

3710f

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