TMC22071A Ver la hoja de datos (PDF) - Fairchild Semiconductor
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TMC22071A Datasheet PDF : 24 Pages
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TMC22071A
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Number
68 pin 100 pin
Pin Name PLCC MQFP
Digital Video
GHSYNC 12
32
GVSYNC 13
33
CVBS7-0 11-9, 6- 30-28,
2
25-21
mP l/O
D0
66
9
A0
60
1
CS
62
5
RESET
64
7
R/W
61
4
INT
VALID
67
17
14
34
Pin Type
CMOS
CMOS
CMOS
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Function
Horizontal sync output. When the TMC22071A is locked to
incoming video, the GHSYNC pin provides a negative-going pulse
after the falling edge of the horizontal sync pulse. There is a fixed
number of PXCK clock cycles between adjacent falling edges of
GHSYNC, except following a VCR headswitch.
Vertical sync output. When the TMC22071A is locked to incoming
video, the GVSYNC pin provides a negative-going edge after the
start of the first vertical sync pulse of a vertical blanking interval.
Composite output bus. 8-bit composite video data is output on this
bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier
frequency, and subcarrier phase are available on this bus.
Data l/O port. Microprocessor data port. All control parameters are
loaded into and read back from the Control Register over this 1-bit
bus.
mP port control. Microprocessor address bus. A LOW on this input
loads the l/O Port Shift Register with data from D0 and CS. A HIGH
transfers the l/O Port Shift Register contents into the Control Register
on the last falling edge of CS.
Chip select. When CS is HIGH, D0 is in a high-impedance state and
ignored. When CS is LOW, the microprocessor can read or write D0
data into the Control Register.
Master reset input. Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC22071A in its default mode.
Bus read/write control. When R/W and A0 are LOW, the
microprocessor can write to the Control Register over D0. When R/W
is HIGH and A0 is LOW, the contents of the Status Register are read
over D0.
Interrupt output. This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
HSYNC locked flag. This output, when HIGH indicates that
incoming horizontal sync has been detected within the ±16 pixel
window in time established by previous sync pulses. When LOW, it
indicates that incoming horizontal sync has not been found within the
expected time frame. VALID will toggle if the time stability of
incoming video is such that sync positioning varies more than
±16 pixels or if occasional horizontal sync pulses are missing.
5
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