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LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Dual D-type flip-flop with set and reset;

positive edge-trigger

Product specification

74LV74

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V v 3.6V

VM = 0.5 * VCC at VCC t 2.7V and w 4.5V

VOL and VOH are the typical output voltage drop that occur with the

output load.

VI

ÏÏÏ nD INPUT

VM

ÏÏÏ GND

tsu

VI

nCP INPUT

GND

VOH

nQ OUTPUT

VOL

VOH

nQ OUTPUT

VOL

ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏ

th

th

tsu

1/fmax

VM

tW

tPHL

tPLH

VM

VM

tPLH

tPHL

SV00335

Figure 1.The clock (nCP) to output (nQ, nQ) propagation

delays, the clock pulse width, the nD to nCP setup times, the

nCP to nD hold times, the output transition times and the

maximum clock pulse frequency

NOTE:

The shaded areas indicate when the input is permitted to change for

predictable output performance.

VI

nCP INPUT

GND

VI

nSD INPUT

GND

VI

nRD INPUT

GND

VOH

nQ OUTPUT

VOL

VOH

nQ OUTPUT

VOL

VM

tW

tPLH

VM

VM

tPHL

VM

trem

tW

VM

tPHL

tPLH

TEST CIRCUIT

Vcc

PULSE

GENERATOR

Vl

RT

D.U.T.

VO

50pF

CL

RL= 1k

Test Circuit for Outputs

DEFINITIONS

RL = Load resistor

CL = Load capacitance includes jig and probe capacitiance

RT = Termination resistance should be equal to ZOUT of pulse generators.

TEST

tPLH/tPHL

VCC

< 2.7V

2.7–3.6V

≥ 4.5 V

VI

VCC

2.7V

VCC

SV00902

Figure 3. Load circuitry for switching times

SV00336

Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ)

propagation delays, the set and reset pulse widths and the nRD

to nCP removal time

1998 Apr 20

7

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