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7641

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

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MITSUBISHI MICROCOMPUTERS

7641 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

UART Address Mode

The UART address mode is intended for use to communicate be-

tween the specified MCUs in a multi-MCU environment. The

UART address mode can be used in either an 8-bit or 9-bit char-

acter length. An address is identified by the MSB of the incoming

data being “1”. The bit is “0” for non-address data.

When the MSB of the incoming data is “0” in the UART address

mode, the Receive Buffer Full Flag is set to “1”, but the Receive

Buffer Full Interrupt Request Bit is not set to “1”. When the MSB of

the incoming data is “1”, normal receive operation is performed. In

the UART address mode an overrun error is not detected for re-

ception of the 2nd and onward bytes. An occurrence of framing

error or parity error sets the Summing Error Interrupt Request Bit

to “1” and the data is not received independent of its MSB con-

tents.

Usage of UART address mode is explained as follows:

(1) Set the UART Address Mode Enable Bit to “1”.

(2) Sends the address data of a slave MCU first from a host MCU

to all slave MCUs. The MSB of address data must be “1” and

the remaining 7 bits specify the address.

(3) The all slave MCUs automatically check for the received data

whether its stop bit is valid or not, and whether the parity error

occurs or not (when the parity enabled). If these errors occur,

the Framing Error Flag or Parity Error Flag and the Summing

Error Flag are set to “1”. Then, the Summing Error Interrupt

Request Bit is also set to “1”.

(4) When received data has no error, the all slave MCUs must

judge whether the address of the received address data

matches with their own addresses by a program. After the

MSB being “1” is received, the UART Address Mode Enable

Bit is automatically set to “0” (disabled).

(5) The UART Address Mode Enable Bit of the slave MCUs which

have be judged that the address does not match with them

must be set to “1” (enabled) again by a program to disable re-

ception of the following data.

(6) Transmit the data of which MSB is “0” from the host MCU. The

slave MCUs disabling the UART address mode receive the

data, and their Receive Buffer Full Flags and the Receive

Buffer Full Interrupt Request Bits are set to “1”. For the other

slave MCUs enabling the UART address mode, their Receive

Buffer Full Flag are set to “1”, but their Receive Buffer Full In-

terrupt Request Bits are not set to “1”.

(7) An overrun error cannot be detected after the first data has

been received in UART Address Mode. Accordingly, even if

the slave MCUs does not read the received data and the next

data has been received, an overrun error does not occur.

Thus, a communication between a host MCU and the specified

MCU can be realized.

[UARTx (x = 1, 2) Mode Register (UxMOD)] 003016, 003816

The UART x mode register consists of 8 bits which set a transfer

data format and an used clock.

[UARTx (x = 1, 2) Baud Rate Generator (UxBRG)] 003116,

003916

The UARTx baud rate generator determines the baud rate for

transfer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

The reset cannot affect the contents of baud rate generator.

[UARTx (x = 1, 2) Status Register (UxSTS)] 003216, 003A16

The read-only UARTx status register consists of seven flags (bits

0 to 6) which indicate the UART operating status and various er-

rors.

When the UART address mode is enabled , the setting and clear-

ing conditions of each flag differ from the following explanations.

These differences are explained in section “UART Address

Mode”.

•Transmit complete flag (TCM)

In the case where no data is contained in the transmit buffer reg-

ister, the Transmit Complete Flag (TCM) is set to “1” when the last

bit in the transmit shift register is transmitted.

The TCM flag is also set to “1” at reset or initialization by setting

the Transmit Initialization Bit (bit 2 of UxCON). It is set to “0” when

transmission starts, and it is kept during the transmission.

•Transmit buffer empty flag (TBE)

The Transmit Buffer Empty Flag (TBE) is set to “1” when the con-

tents of the transmit buffer register are loaded into the transmit

shift register. The TBE flag is also set “1” at the hardware reset or

initialization by setting the Transmit Initialization Bit. It is set to “0”

when a write operation is performed to the low-order byte of the

transmit buffer register.

•Receive buffer full flag (RBF)

The Receive Buffer Full Flag (RBF) is set to “1” when the last stop

bit of the data is received. The RBF flag is set to “0” when the low-

order byte of the receive buffer register is read, at the hardware

reset or initialization by setting the Transmit Initialization Bit.

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