M62055FP
Block Diagram
VCC
8
–
Rise delay
+
(300µs)
Vref
≈1.25V
+
–
Vref
≈1.5V
CLM
7
VCC
VD
6
VCC
VCC
Voltage detector
(Current limiter)
Start circuit
The input and output
reversal conservation
circuit
–
+
–
+
Vref
≈1.5V
Set
priority
RQ
SQ
VCC
+
–
Vref
≈0.9V
Reset
priority
RQ
SQ
Reset
priority
SQ
RQ
Reset
priority
RQ
SQ
–
+
+
–
VO
5
56k
40k
Vref
=1.25V
Set
priority
SQ
RQ
1
2
3
GND
WD
TC
Note: It indicates VO, unless otherwise noted.
4
RESET
Pin Functional Description
Pin No.
1
2
3
4
5
6
Symbol
GND
WD
TC
RESET
VO
VD
7
CLM
8
VCC
Functional Description
Ground
Input for watchdog timer
Setting up reset timer and watchdog timer
Reset signal output
Feedback to a power supply for a MCU
Controlling the stability of an output voltage with a PNP transistor connected
externally
Current limiting
Power supply voltage
Rev.2.00 Mar 10, 2006 page 2 of 9