![](/html/Motorola/758706/page5.png)
tr
tf
CLOCK
Q
90%
50%
10%
tw
90%
50%
10%
1/fmax
tPLH
tPHL
tTLH
tTHL
Figure 1.
SWITCHING WAVEFORMS
MC54/74HC574A
VCC
3.0 V
1.3 V
GND
GND
tPZL tPLZ
HIGH
Q
1.3 V
tPZH tPHZ
IMPEDANCE
10% VOL
90% VOH
Q
HIGH
IMPEDANCE
Figure 2.
DATA
CLOCK
VALID
VCC
50%
GND
tsu
th
VCC
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
EXPANDED LOGIC DIAGRAM
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
CLOCK 11
OUTPUT ENABLE 1
* Includes all probe and jig capacitance
Figure 5. Test Circuit
High–Speed CMOS Logic Data
3–5
DL129 — Rev 6
MOTOROLA