MC74VHC240(2001) Ver la hoja de datos (PDF) - ON Semiconductor
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MC74VHC240 Datasheet PDF : 8 Pages
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ON Semiconductort
Octal Bus Buffer/Line Driver
Inverting with 3-State Outputs
The MC74VHC240 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC240 is an inverting 3–state buffer, and has two
active–low output enables. This device is designed to drive bus lines
or buffer memory address registers.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 3.6ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.9V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 120 FETs or 30 Equivalent Gates
A1 2
A2 4
A3 6
DATA
INPUTS
A4 8
B1 11
B2 13
B3 15
B4 17
18 YA1
16 YA2
14 YA3
12 YA4
9 YB1
INVERTING
OUTPUTS
7 YB2
5 YB3
3 YB4
OUTPUT OEA 1
ENABLES OEB 19
Figure 1. LOGIC DIAGRAM
© Semiconductor Components Industries, LLC, 2001
1
March, 2001 – Rev. 3
MC74VHC240
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–05
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCXXXDW SOIC WIDE
MC74VHCXXXDT TSSOP
MC74VHCXXXM
SOIC EIAJ
OEA 1
A1 2
YB4 3
A2 4
YB3 5
A3 6
YB2 7
A4 8
YB1 9
GND 10
20 VCC
19 OEB
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
Figure 1. PIN ASSIGNMENT
FUNCTION TABLE
INPUTS
OEA, OEB
A, B
L
L
L
H
H
X
OUTPUTS
YA, YB
H
L
Z
Publication Order Number:
MC74VHC240/D
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