MH8S72BAFD-8 Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
Número de pieza
componentes Descripción
Lista de partido
MH8S72BAFD-8 Datasheet PDF : 56 Pages
| |||
MH8S72BAFD -7, -8 MITSUBISHI LSIs
P rSepl iemci.n a r y 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table
Byte
0
1
2
3
4
5
6
7
8
9
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -7
Cycle time for CL=3
-8
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A8
1BANK
x72
0
LVTTL
10ns
SPD DATA(hex)
80
08
04
0C
09
01
48
00
01
A0
10
SDRAM Access from Clock
tAC for CL=3
-7
-8
6ns
60
11
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
x8
08
15 Minimum Clock Delay,Back to Back Random Column Addresses
1
01
16
Burst Lengths Supported
1/2/4/8/FP
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
19
CS# Latency
20
Write Latency
CL=2/3
06
0
01
0
01
21
SDRAM Module Attributes
Registered and Buffered
1B
22
SDRAM Device Attributes:General
Precharge All,Auto precharge,sw/br
0E
23
SDRAM Cycle time(2nd highest CAS latency)
-7
10ns
A0
Cycle time for CL=2
-8
13ns
D0
24
SDRAM Access form Clock(2nd highest CAS latency) -7
6ns
60
tAC for CL=2
-8
7ns
70
25
SDRAM Cycle time(3rd highest CAS latency)
-7
N/A
00
Cycle time for CL=
-8
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency) -7
N/A
00
tAC for CL=
-8
N/A
00
MIT-DS-0273-0.2
MITSUBISHI
ELECTRIC
1/ Dec./1998 4
Share Link: 