MT8888C Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT8888C Datasheet PDF : 25 Pages
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MT8888C
Data Sheet
FLOW
697
FHIGH
1209
DIGIT
1
D3
D2
D1
D0
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
Table 1 - Functional Encode/Decode Table
Note: 0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
4.0 Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering
flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
5
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