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25L1605ZM

16M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY

Macronix International 

MX25L1605ZM

HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation

of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial

Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock

signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is

being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

SCLK

HOLD#

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during

the HOLD operation. If Chip Select (CS#) signal goes high during HOLD operation, it has the effect on resetting the internal

logic of the device. It is necessary to drive HOLD# signal to high, and then to drive CS# to low for restarting communication

with the device.

The HOLD operation is not recommended to use during parallel mode.

PROGRAM/ERASE ACCELERATION

To activate the program/erase acceleration function requires ACC pin connecting to 12V voltage (see Figure 2), and then

to be followed by the normal program/erase process. By utilizing the program/erase acceleration operation, the

performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".

Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM

12V

VHH

ACC

VIL or VIH

tVHH

tVHH

VIL or VIH

Note: tVHH (VHH Rise and Fall Time) min. 250ns

P/N: PM1291

6

REV. 1.0, MAY 16, 2006

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