P2V28S20ATP-7 Ver la hoja de datos (PDF) - Vanguard International Semiconductor
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P2V28S20ATP-7 Datasheet PDF : 51 Pages
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128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
&Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
MNEMONIC CKE CKE /CS /RAS /CAS /WE BA0,1 A1 1 A1 0 A0-9
n-1 n
DESEL
H
X
HX
XX
X
X
X
X
NOP
H
X
L
H
H
H
X
X
X
X
ACT
H
X
L
L
HH
V
V
V
V
PRE
PREA
H
X
L
L
HL
V
X
L
X
H
X
L
L
HL
X
XHX
WRIT E
H
X
L
H
L
L
V
V
L
V
WRITE A
READ
HX
HX
LH
LH
L
L
V
LHV
VHV
V
L
V
READA
REFA
H
X
L
H
L
H
V
V
HV
H
H
L
L
L
H
X
XX
X
REFS
H
L
L
L
L
H
X
XX
X
REFSX
L
HHX
XX
X
XX
X
L
H
L
H
HH
X
XX
X
Burst Terminate
TBST
HX
L
HHL
XX
XX
Mode Register Set
MR S
H
X
L
L
L
L
L
L
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
JULY.2000
Page-6
Rev.2.2
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