NXP Semiconductors
PHB47NQ10T
N-channel TrenchMOS standard level FET
120
Pder
(%)
80
03aa16
40
0
0
50
100
150
200
Tmb (°C)
102
IAS
(A)
10
003aaa098
25 °C
Tj prior to avalanche = 150 °C
1
10−3
10−2
10−1
1
10
tp (ms)
Fig 3. Normalized total power dissipation as a
function of mounting base temperature
Fig 4. Non-repetitive avalanche ruggedness current
as a function of pulse duration
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from see Figure 5
junction to mounting
base
thermal resistance from mounted on printed-circuit board;
junction to ambient
minimum footprint
Min Typ Max Unit
-
-
0.9 K/W
-
50
-
K/W
1
Zth (j-mb)
(K/W)
10−1
10−2
δ=
0.5
0.2
0.1
0.05
0.02
Single pulse
003aaa099
P
δ = tp
T
10−3
10−7
10−6
10−5
10−4
10−3
10−2
tp
t
T
10−1
1
10
tp (s)
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHB47NQ10T_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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