PSB4596 Ver la hoja de datos (PDF) - Siemens AG
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PSB4596 Datasheet PDF : 104 Pages
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PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
VDD=VDDA= 5V± 5%; TA= 0 - 70°C
Parameter
Symbol
Limit Values
Unit
min
typ
max
Clock cycle time
tc(DCLK) 1/1024
1
ms
Clock duty cycle
45
50
55
%
Setup time, CS↓ before
tsu(CS)
50
ns
DCLK↓
2*tclk1)
Hold time, CS↑ after DCLK↓
thd(CS)
120
ns
Setup time, DIN before
tsu(DIN)
60
ns
DCLK↓
Hold time, DIN after DCLK↓
thd(DIN)
120
ns
Delay time, DCLK↑, to DOUT tpd(DOUT)
100
ns
Delay time, CS↑ to DOUTZ tpd(DOUTZ)
100
ns
1) tclk=1/fclk
Table 31: Control Interface Switching Characteristics
12.5.4 Data Interface Timing
t w (F S C )
t c (F S C )
FSC
t p d (F S C )
t c (D A T _ C L K )
t id le (F S C )
D A T_C LK
t s u (D A T _ IN )
D A T _ IN
t h d (D A T _ IN )
t p d (D A T _ O U T )
DAT O UT
Figure 46 Data Interface Timing
Semiconductor Group
102
Data Sheet 06.98
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