PSB4595 Ver la hoja de datos (PDF) - Siemens AG
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PSB4595 Datasheet PDF : 104 Pages
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PSB 4595 / PSB 4596
Analog Line Interface Solution
Electrical Performance Characteristic
VDD=VDDA= 5V± 5%; TA=0 - 70°C
Parameter
Data clock cycle time
Data clock duty cycle
Frame synch clock cycle time
FSC pulse width (as input)
FSC pulse width (as output)1)
Setup time, DAT_IN before
DAT_CLK↓
Hold time, DAT_IN after
DAT_CLK↓
Delay time, DAT_CLK↑ to
DAT_OUT
Idle time, DAT_CLK↓ to FSC↑
Delay time, DAT_CLK↑ to FSC↑
Setup time, FSC↑ to DAT_CLK↓
Symbol
Limit Values
Unit
min typ max
tc(DAT_CLK) 1/
1024
1/ ms
128
45
50 55
%
tc(FSC)
125
µs
tw(FSC)
488
ns
tw(FSC)
tclk*20
µs
tsu(DAT_IN) 50
ns
thd(DAT_IN) 100
180 ns
tpd(DAT_OUT)
100 ns
tidle(FSC)
488
ns
tpd(FSC)
0
ns
tsu(FSC) tclk+60
ns
1) Guaranteed by design
Table 32: Data Interface Switching Characteristics
Semiconductor Group
103
Data Sheet 06.98
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