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PSB4595

Analog Line Interface Solution ALIS

Siemens AG 

PSB 4595 / PSB 4596

Analog Line Interface Solution

Pin Definition and Functions

2.3 Pin Definition of ALIS-D PSB 4596

Pin No.

8

9

25

24

21

20

23

15

17

16

18

10

Symbol

VDD

GND

VDDA

GNDA

MCLK1

Function

Power

Power

Power

Power

I

MCLK2

O

RESET

I

FSC

BI

DAT_IN / I

SEL

DAT_OUT O

DAT_CLK I

CS

I

Description

+5 Volt supply for the digital circuitry

Ground digital: All signals are referred to

this pin

+5 Volt supply for the analog circuitry

Ground analog: All analog signals are

referred to this pin

Master clock1: One pin of a crystal or

ceramic resonator is connected. This pin

can also be driven from an external

clocking source of 16.384 MHz,

synchronous to FSC (MCLK=FSC*2048)

Master clock2: The other pin of a crystal or

ceramic resonator is connected. When

MCLK1 is driven by an external clock, this

pin should be left open

Reset input: Forces the device to default

mode (low active)

As input: Frame synchronisation clock,

8kHz, identifies the beginning of the

frame. FSC must be synchronous to

MCLK (MCLK=FSC*2048)

As Output: Indicates the beginning of a

new frame

Data interface: Receive data from the

DSP. The data is received in 16-bit bursts

every 125 ms.

Interface selection pin in MUX mode.

Data interface: Transmit data to the DSP.

The data is transmitted in 16-bit bursts

every 125 ms

Data clock 128 to 1024 kHz: Determines

the rate at which data is shifted into or out

of the data interface

µ-controller interface: Chip select enable

to read or write data. Active low

Semiconductor Group

13

Data Sheet 06.98

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