RMWB33001 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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RMWB33001 Datasheet PDF : 6 Pages
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Electrical Characteristics (At 25°C), 50Ω system, Vd = +4V, Quiescent Current Idq = 112mA
Parameter
Frequency Range
Gate Supply Voltage1 (Vg)
Gain Small Signal (Pin = -15dBm)
Gain Variation vs. Frequency
Power Output Saturated: (Pin = +1dBm)
Drain Current at Psat
Power Added Efficiency (PAE): at Psat
Input Return Loss (Pin = -15dBm)
Output Return Loss (Pin = -15dBm)
DC Detector Voltage at Pout = 18dBm
Min
Typ
Max
32
35
-0.2
20
24
2.0
17
19
120
15
12
12
1.0
Note:
1: Typical range of gate voltage is -0.5 to 0V to set Idq of 112mA.
Units
GHz
V
dB
dB
dBm
mA
%
dB
dB
V
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
Chip carrier material should be selected to have GaAs
compatible thermal coefficient of expansion and high
thermal conductivity such as copper molybdenum or copper
tungsten. The chip carrier should be machined, finished flat,
plated with gold over nickel and should be capable of
withstanding 325°C for 15 minutes.
Die attachment should utilize Gold/Tin (80/20) eutectic alloy
solder and should avoid hydrogen environment for PHEMT
devices. Note that the backside of the chip is gold plated
and is used as RF and DC ground.
These GaAs devices should be handled with care and
stored in dry nitrogen environment to prevent contamination
of bonding surfaces. These are ESD sensitive devices and
should be handled with appropriate precaution including the
use of wrist grounding straps. All die attach and wire/ribbon
bond equipment must be well grounded to prevent static
discharges through the device.
Recommended wire bonding uses 3 mils wide and 0.5 mil
thick gold ribbon with lengths as short as practical allowing
for appropriate stress relief. The RF input and output bonds
should be typically 0.012" long corresponding to a typical 2
mil gap between the chip and the substrate material.
Drain Supply Drain Supply Drain Supply Drain Supply
Vd1
Vd2
Vd3
Vd4
MMIC Chip
RF IN
RF OUT
Ground
(Back of Chip)
Gate Supply
Vg
Output Power
Detector Voltage
Vdet
Figure 1. Functional Block Diagram1
Note:
1: Detector delivers >0.1V DC into 3kΩ load resistor for > +18dBm output power. If output power level detection is not desired, do not connect to detector bond pad.
©2004 Fairchild Semiconductor Corporation
RMWB33001 Rev. C
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