RTL8305S Ver la hoja de datos (PDF) - Unspecified
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RTL8305S Datasheet PDF : 24 Pages
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RTL8305S
5.3 Port4 Related Pins
Pin Name
MRXD[3:0]
/MTXD[3:0]
MRXDV/MTXEN
MRXC/MTXC
MCOL
MTXD[3:0]
/MRXD[3:0]
MTXEN/MRXDV
MTXC/MRXC
P4MODE[1:0]
P4LNKSTA#
P4DPXSTA#
P4SPDSTA#
P4FLCTRL#
ENP4LED
SEL_MIIMAC#
Pin No.
67,66,63
61
60
59
58
57,56,55
54
52
51
97,98
49
Type
Description
Default
I For MII MAC mode, these pins are MRXD[3:0], MII receive data nibble.
For MII PHY mode, these pins are MTXD[3:0], MII transmit data nibble.
For SNI PHY mode, MTXD[0] is serial transmit data.
I For MII MAC mode, this pin represents MRXDV, MII receive data valid.
For MII PHY mode, this pin represents MTXEN, MII transmit enable.
I/O For MII MAC mode, it is receive clock, MRXC (acts as input).
For MII/SNI PHY mode, it is transmit clock, MTXC (acts as output).
I/O For MII MAC mode, this pin represents collision (acts as input)
For MII/SNI PHY mode, this pin represents collision (acts as output)
O For MII MAC mode, these pins are MTXD[3:0], MII transmit data nibble.
For MII PHY mode, these pins are MRXD[3:0], MII receive data nibble.
For SNI PHY mode, MRXD[0] is serial receive data.
O For MII MAC mode, this pin represents MTXEN, MII transmit enable.
For MII PHY mode, this pin represents MRXDV, MII receive data valid.
I/O For MII MAC mode, this pin is a transmit clock, MTXC (acts as input).
For MII/SNI PHY mode, this pin is a receive clock, MRXC (acts as output).
I Select Port 4 Operating Mode: 00: SNI PHY mode
11
01: MII PHY mode
1x: UTP / MII MAC mode
I Port 4 Link Status: When P4MODE[1]=1 (UTP/MII MAC mode), this 1
pin decides the link status of the MII port. If both UTP and MII MAC are
linked OK, UTP has higher priority.
When P4MODE[1]=0 (PHY mode), this pin decides link status of Port4.
48
I Active Low Duplex Status:
1: Half duplex
1
0: Full duplex
When P4 is operated in UTP mode, this pin has no effect.
47
I Active Low Speed Status:
1: 10Mbps
1
0: 100Mbps
This pin must be kept floating for the three applications listed below.
This is because the speed is either determined by auto-negotiation or
fixed at 1M/10M Hz.
1. For UTP mode, speed is determined by the auto-negotiation procedure.
2. For HomePNA (MII MAC mode), speed is determined by RXC and
TXC from HomePHY running at 1Mbps.
3. For SNI PHY mode, speed is dedicated to 10MHz clock rate.
46
I Active Low Flow Control Enable: When P4 is operated in UTP mode, 1
this pin has no effect.
1: Disable
0: Enable
91
I Enable Port 4 LED: In UTP applications, this pin should be floating to 1
drive the LEDs of port 4.
1: Drive LED pins of port4
0: Tri-state LED pins of port4
68
O Select MII MAC: When P4MODE[1]=1, this pin indicates whether UTP
path or MII MAC path is selected.
1: UTP is selected
0: MII port is selected
While P4MODE[1]=1, the RTL8305S supports UTP/MII MAC auto-detect
function via the link status of P4 UTP and the status of P4LINKSTA# with
priority UTP over MII.
2002/02/19
7
Rev. 1.2
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