GS880E32T-66I Ver la hoja de datos (PDF) - Giga Semiconductor

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GS880E32T-66I

512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs

Giga Semiconductor 

Write Cycle Timing

Preliminary

GS880E18/32/36T-11/11.5/100/80/66

CK

ADSP

ADSC

ADV

A0–An

GW

BW

BA–BD

E1

E2

E3

G

DQA–DQD

Single Write

Burst Write

Write

Deselected

tS tH

tS tH

tKH tKL tKC ADSP is blocked by E inactive

ADSC initiated write

tS tH

tS tH ADV must be inactive for ADSP Write

WR1

WR2

WR3

tS tH

tS tH

tS tH

tS tH

WWRR11

WR2

E1 masks ADSP

WWRR33

tS tH

tS tH

E2 and E3 only sampled with ADSP or ADSC

Deselected with E2

Hi-Z

tS tH

D1A

Write specified byte for 2A and all bytes for 2B, 2c& 2D

D2A

D2B

D2C

D2D

D3A

Rev: 1.11 11/2000

16/25

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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