GS880E32T-100 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS880E32T-100

512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs

Giga Semiconductor 

Preliminary

GS880E18/32/36T-11/11.5/100/80/66

Pipelined DCD Read Cycle Timing

CK

ADSP

ADSC

ADV

A0–An

GW

BW

Single Read

Burst Read

tKL

tS tH

tKH

tKC ADSP is blocked by E1 inactive

tS tH

ADSC initiated read

tS tH

Suspend Burst

tS tH

RD1

RD2

tS

RD3

tH

tS

tH

BA–BD

E1

E2

E3

G

DQA–DQD

tS tH

tS tH

tS tH

E1 masks ADSP

E2 and E3 only sampled with ADSP or ADSC

tOE

tOHZ

tKQX

tOLZ

Hi-Z

Q1A

Q2A Q2B

Q2c

tLZ

tKQ

Deselected with E2

tKQX

Q2D Q3A

tHZ

Rev: 1.11 11/2000

19/25

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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