GS880E36T-11.5 Ver la hoja de datos (PDF) - Giga Semiconductor
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GS880E36T-11.5 Datasheet PDF : 25 Pages
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Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H or NC
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, IDD = ISB
Note:
There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address 01 10 11 00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.11 11/2000
7/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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