U5021M-NFPY Ver la hoja de datos (PDF) - Atmel Corporation

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U5021M-NFPY

Digital Window Watchdog Timer

Atmel Corporation 

U5021M

3. Pin Description

Pin

Symbol Function

Wake-up input (pull-down resistor)

1

WAKE-UP There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at

the input initiates a reset pulse at pin 5.

2

TRIG

Trigger input (pull-up resistor)

It is connected to the microprocessor’s trigger signal.

3

MODE

Mode input (pull-up resistor)

The processor’s mode signal initiates the switchover between the long and the short watchdog time.

Enable output (push-pull)

4

ENA

It is used for the control of peripheral components. It is activated after the processor triggers three times

correctly.

Reset output (open drain)

5

RESET Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog

period.

6

VDD

Supply voltage

7

GND

Ground, reference voltage

8

OSC

RC oscillator

4. Functional Description

4.1 Supply Voltage, Pin 6

The U5021M requires a stabilized supply voltage VDD = 5 V ±5% to comply with its electrical

characteristics.

An external buffer capacitor of C = 10 nF may be connected between pin 6 and GND.

4.2 RC Oscillator, Pin 8

The clock frequency, f, can be adjusted by the components R1 and C1 according to the formula:

f = 1--

t

where t = 1.35 + 1.57 R1 (C1 + 0.01)

R1 in kΩ, C1 in nF and t in µs

The clock frequency determines all time periods of the logic part as shown in the table “Electrical

Characteristics” under the subheading “Timing” on page 9. With an appropriate component

selection, the clock frequency, f, is nearly independent of the supply voltage as shown in Figure

4-1 on page 4.

Frequency tolerance ∆fmax = 10% with R1 ±1%, C1 = ±5%

3

4756D–AUTO–11/05

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