Preliminary
GS88118/36T-11/11.5/100/80/66
Pipelined SCD Read-Write Cycle Timing
CK
ADSP
ADSC
ADV
A0–An
GW
BW
BWA–BWD
E1
Single Read
Single Write
tKL
Burst Read
tS tH
tKH
tKC
ADSP is blocked by E inactive
tS tH ADSC initiated read
tS tH
tS tH
RD1
tS tH
tS
WR1
RD2
tH
tS tH
tS tH
WR1
E1 masks ADSP
tS tH
E2 only sampled with ADSP and ADSC
E2
G
Hi-Z
DQA–DQD
tOE tOHZ
tKQ
Q1A
tS tH
D1A
Q2A
Q2B
Q2c Q2D
Rev: 1.11 9/2000
20/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.