GS88136T-66 Ver la hoja de datos (PDF) - Giga Semiconductor
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GS88136T-66 Datasheet PDF : 33 Pages
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Preliminary
GS88118/36T-11/11.5/100/80/66
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
16
66
87
93, 94
95, 96
95, 96
89
88
98
97
86
83
84, 85
Symbol
Typ
e
A0, A1
I
A2–A17
I
A18
I
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
I/O
DQD1–DQD8
DQA9, DQB9,
DQC9, DQD9
I/O
DQA1–DQA9
DQB1–DQB9
I/O
NC
—
DP
I
QE
O
BW
I
BA, BB
I
BC, BD
I
NC
—
CK
I
GW
I
E1
I
E2
I
G
I
ADV
I
ADSP, ADSC I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs
Data Input and Output pins ( x36 Version)
Data Input and Output pins
Data Input and Output pins
No Connect
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low ( x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Rev: 1.11 9/2000
4/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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